Paper 2 CS · UNIT 02 · MOCK TEST

Computer System Architecture — Mock Test 4

25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.

0 / 25 answered 00:00

Q1. Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1 + R2, which values of R1 and R2 give an arithmetic overflow?

AR1 = 1011 and R2 = 1110 BR1 = 1100 and R2 = 1010 CR1 = 0011 and R2 = 0100 DR1 = 1001 and R2 = 1111

Q2. Consider the Boolean expression F = (X + Y + Z)(X′ + Y)(Y′ + Z). Which of the following Boolean expressions is/are equivalent to F′ (the complement of F)?
A. (X′ + Y′ + Z′)(X + Y′)(Y + Z′)
B. XY′ + Z′
C. (X + Z′)(Y′ + Z′)
D. XY′ + YZ′ + X′Y′Z′
Choose the correct answer from the options given below:

AA, B and C Only BB, C and D Only CA, C and D Only DA, B and D Only

Q3. Which of the following statements is/are true?
A. The processor has direct access to both primary and secondary memory.
B. Primary memory stores the active instructions and data of the program being executed.
C. Secondary memory is used as backup memory.
D. The memory system is implemented as a single-level memory.
Choose the correct answer from the options given below:

AA and B only BB and C only CA, B and C only DA and D only

Q4. Match List I (8085 instructions) with List II

List I	List II
A. DAA	I. Program Control Instruction
B. LXI	II. Interrupt instruction
C. RST	III. Data Movement Instruction
D. JMP	IV. Arithmetic Instruction

AA-IV, B-II, C-I, D-III BA-IV, B-III, C-II, D-I CA-IV, B-II, C-III, D-I DA-III, B-IV, C-II, D-I

Q5. The sequence of events during a typical instruction fetch is:
A. Memory
B. MBR
C. MAR
D. PC
E. IR
Choose the correct order from the options given below:

AA, B, C, D, E BD, C, A, B, E CE, D, C, B, A DD, C, A, E, B

Q6. Which one of the following types of memory is the fastest?

ACache Memory BRegister Memory CMain Memory DSecondary Memory

Q7. The memory size for n address lines and m data lines is given by

A2^m × n Bm × n² C2ⁿ × m Dn × m²

Q8. Simplify the following using a K-map: F(A, B, C, D) = Σ(0, 2, 5, 7, 8, 10, 13, 15)

ABD + B′D′ BAC + A′C′ CBC + B′C′ DAD + A′D′

Q9. Consider an unpipelined machine with 10 ns clock cycles which uses four cycles for ALU operations and branches, and five cycles for memory operations. The relative frequencies of these operations are 40%, 20% and 40% respectively. Due to clock skew and setup, the pipelined machine adds 1 ns overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered?

A2 times B4 times C6 times D8 times

Q10. Which of the statements is not true in regard to virtual memory?

AThe main objective of using virtual memory is to increase the effective capacity of the memory system BSize of the program can be as large as the size of the secondary memory CProgram and data are stored in the secondary memory DNone of these

Q11. Which of the following is/are true for Dynamic RAM (DRAM)?
1. It is slower than static RAM (SRAM)
2. Packing density is higher than static RAM (SRAM)
3. It is faster than static RAM (SRAM)
4. It requires data refreshing
Choose the correct answer from the options given below:

A1, 2 and 4 only B1, 2 and 3 only C3 and 4 only D2 and 4 only

Q12. Which of the following statements is/are false?
1. The processor has direct access to both primary and secondary memory
2. Primary memory stores the active instructions and data for the program being executed on the processor
3. Secondary memory is used as a backup memory
4. A memory system is implemented on a single-level memory
Choose the correct answer from the options given below:

A1 and 2 only B2 and 3 only C1, 2 and 3 only D1 and 4 only

Q13. Match List I with List II (8085 addressing modes).
Choose the correct answer from the options given below:

List I	List II
a. Direct addressing	I. MVI A, FFH
b. Indirect addressing	II. MOV A, B
c. Register addressing	III. STA FFFFH
d. Immediate addressing	IV. MOV A, M

Aa-I, b-II, c-III, d-IV Ba-II, b-III, c-IV, d-I Ca-III, b-IV, c-II, d-I Da-IV, b-III, c-I, d-II

Q14. The correct sequence in the fetch–execute cycle is ______.
I. Decode
II. Fetch
III. Execute

AI-II-III BII-III-I CIII-II-I DII-I-III

Q15. Consider a memory system with addresses spaced at a distance of m (stride), T = bank cycle time and n = number of banks. Then the average data access time per word in a synchronous (interleaved) organisation is

At = m·T/n for m ≪ n; t = T for m ≫ n Bt = T/n for m ≪ n; t = T for m ≫ n Ct = m·T for m ≪ n; t = T for m ≫ n Dt = m·T for m ≪ n; t = m/T for m ≫ n

Q16. In a multiprocessor system, the crossbar switch interconnection network is an example of a

ANon-blocking network BBlocking network CNetwork that varies from connection to connection DRecurrent network

Q17. The representation of the 4-bit code 1101 as a 7-bit even-parity Hamming code is

A1010101 B1111001 C1011101 D1110000

Q18. The number of gate inputs required to realise the expression ABC + AB′CD + EF′ + AD is

A12 B13 C14 D15

Q19. Consider a logic circuit with 8 input lines (D0, D1, …, D7) and 3 output lines (A0, A1, A2) specified by:
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D0
where + is logical OR. This circuit is a(n)

A3 × 8 multiplexer BDecimal to BCD converter COctal to binary encoder DPriority encoder

Q20. The total storage capacity of a floppy disk having 80 tracks and storing 128 bytes/sector is 163,840 bytes. How many sectors does this disk have (per track)?

A2⁷ B2048 C4K D16

Q21. In a cache memory, if the address has 9 bits in the tag field and 12 bits in the index field, the sizes of main memory and cache memory would be, respectively,

A2K, 4K B1024K, 2K C4K, 2048K D2048K, 4K

Q22. A 4-stage pipeline has stage delays of 150, 120, 160 and 140 ns. Registers between the stages have a delay of 5 ns. Assuming a constant clocking rate, the total time required to process 1000 data items is

A160.5 μs B165.5 μs C120.5 μs D590.5 μs

Q23. Match List I with List II.
Choose the correct answer from the options given below:

List I	List II
A. Stack overflow	I. Software interrupt
B. Timer	II. Internal interrupt
C. Invalid opcode	III. External interrupt
D. Supervisor call	IV. Machine check interrupt

AA-I, B-II, C-III, D-IV BA-II, B-III, C-I, D-IV CA-I, B-II, C-IV, D-III DA-II, B-III, C-IV, D-I

Q24. A magnetic tape drive has a transport speed of 200 inches per second and a recording density of 1600 bytes per inch. The time required to write 600000 characters of data grouped into 100-character records with a blocking factor of 10 is

A1.875 sec B2.6251 sec C2.0062 sec D2.6150 sec

Q25. Statement I: Consider the 20-bit 'branch' microinstruction format: F1 (3 bits) | F2 (3) | F3 (3) | CD (2) | BR (2) | AD (7), where F1, F2, F3 are micro-operation fields, CD = condition for branching, BR = branch field and AD = address field.
Statement II: An instruction in the above format can branch on 4 conditions.
Choose the most appropriate answer.

ABoth Statement I and Statement II are correct BBoth Statement I and Statement II are incorrect CStatement I is correct but Statement II is incorrect DStatement I is incorrect but Statement II is correct