Paper 2 CS · UNIT 02 · MOCK TEST

Computer System Architecture — Mock Test 3

25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.

0 / 25 answered 00:00

Q1. The average time required to reach a storage location in memory and obtain its contents is called:

AAccess time BLatency time CResponse time DReading time

Q2. The interface(s) that provide I/O transfer of data directly to and from the memory unit and a peripheral is/are termed:
(A) DMA (Direct Memory Access)
(B) IOP (Input-Output Processor)
(C) Serial Interface
(D) Parallel Interface
Choose the correct answer from the options given below:

A(A) Only B(B) Only C(A) and (B) Only D(C) and (D) Only

Q3. Which of the following is/are main memory?
(A) Virtual memory
(B) Cache memory
(C) RAM
(D) SSD
Choose the correct answer from the options given below:

A(A) and (C) Only B(B) and (C) Only C(C) and (D) Only D(A), (B) and (C) Only

Q4. Which of the following statements is/are NOT CORRECT about NUMA?
(A) LOAD and STORE instructions are used to access remote memory.
(B) There is a single address space visible to all CPUs.
(C) Access to local memory is slower than access to remote memory.
(D) When the access time to remote memory is hidden, the system is called NC-NUMA.
(E) In CC-NUMA, coherent caches are present.
Choose the correct answer from the options given below:

A(A) and (C) Only B(B) and (D) Only C(A) and (E) Only D(C) and (D) Only

Q5. Match List I with List II (basic computer instructions)

List I	List II
(a) SZA	(I) Increment M and skip if zero
(b) SKI	(II) Skip if AC is negative
(c) SNA	(III) Skip if input flag is on
(d) ISZ	(IV) Skip if AC is zero

A(a)-(II), (b)-(IV), (c)-(I), (d)-(III) B(a)-(IV), (b)-(III), (c)-(II), (d)-(I) C(a)-(IV), (b)-(II), (c)-(I), (d)-(III) D(a)-(III), (b)-(IV), (c)-(II), (d)-(I)

Q6. In the most general case, the computer needs to process each instruction with the following sequence of steps:
(A) Calculate the effective address
(B) Execute the instruction
(C) Fetch the instruction from memory
(D) Fetch the operand from memory
(E) Decode the instruction
Choose the correct answer from the options given below:

A(C), (E), (D), (A), (B) B(C), (E), (A), (D), (B) C(A), (B), (C), (E), (D) D(A), (B), (C), (D), (E)

Q7. What is the 4+4-bit binary fixed-point (two's complement) equivalent of −(3.72)₁₀?

A0011.1100 B0011.1010 C1100.0100 D0011.1011

Q8. Let ⊕ denote XOR, and 1 and 0 the binary constants. F(P, Q) = ((1 ⊕ P) ⊕ (P ⊕ Q)) ⊕ ((P ⊕ Q) ⊕ (Q ⊕ 0)). Which of the following is equivalent to F?

AP ⊕ Q BP + Q Ccomplement of (P + Q) Dcomplement of (P ⊕ Q)

Q9. A processor chip is used for an application in which 30% of execution time is spent on floating-point addition. For the new model, the design team redesigns the floating-point adder to make it twice as fast. What is the maximum possible speed-up from this redesign?

A2.0 B1.06 C1.18 D2.5

Q10. A 256 Mb DRAM is organised as a 32M × 8 memory externally and as a 16K × 16K square array internally. Each row must be refreshed at least once every 50 ms, and refreshing one row takes 100 ns. What fraction of the total memory bandwidth is lost to refresh cycles?

A6.6% B3.3% C9.9% D4.3%

Q11. The instruction LD ADR(X), equivalent to AC ← M[ADR + XR], is in:

ADirect addressing mode BIndirect addressing mode CIndex addressing mode DImmediate addressing mode

Q12. The instructions
ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
evaluate X = (A + B) * (C + D) using which of the following?

A3-address instructions B2-address instructions C1-address instructions DRISC instructions

Q13. The Boolean expression for F(A, B, C) = Σm(0, 2, 6) with don't-cares d(A, B, C) = Σ(1, 3, 5) would be:

AA′C′ + BC′ BB + AC′ CA + BC′ DA′ + BC′

Q14. A computer system has a cache access time of 100 ns, a main-memory access time of 1100 ns and a hit ratio of 0.9. The average access time would be:

A200 ns B190 ns C210 ns D120 ns

Q15. Match List I (Boolean expression) with List II (dual of the Boolean expression)

List I	List II
A. x·y + 0	I. (x̄ + 0)·(ȳ·z)
B. x̄·1 + (ȳ + z)	II. (x + y)·1
C. x̄·(ȳ + 0)	III. x̄ + ȳ·1
D. x·1 + (y + z̄)	IV. (x + 0)·(y·z̄)

AA-III, B-IV, C-II, D-I BA-III, B-IV, C-I, D-II CA-II, B-I, C-III, D-IV DA-II, B-I, C-IV, D-III

Q16. The I/O method in which memory addresses and I/O addresses are distinct is called
A. Isolated I/O
B. Memory-mapped I/O
C. Strobe control
D. Handshaking
E. Interrupt
Choose the most appropriate answer from the options given below:

AA, B Only BC, D Only CC, E Only DB, E Only

Q17. Arrange the following from fastest to slowest:
A. DRAM
B. SRAM
C. CPU registers
D. Magnetic tapes
E. Hard disk
Choose the correct answer from the options given below:

AA, B, C, D, E BC, B, A, D, E CC, D, B, A, E DB, C, D, A, E

Q18. Regarding the interrupt service subroutine, consider the following tasks:
A. Turn the interrupt facility on
B. Service the device whose flag is set
C. Save the contents of processor registers
D. Check which flag is set
E. Restore the contents of processor registers
Choose the correct answer from the options given below:

AA, D, C, B, E BD, A, B, C, E CC, D, B, E, A DB, D, A, C, E

Q19. Match List I with List II

List I	List II
A. Complement	I. Adder
B. E-OR	II. Instruction decoding
C. Accumulator	III. Negative number representation
D. Control Unit	IV. Arithmetic and Logic operations

AA-I, B-II, C-III, D-IV BA-III, B-II, C-I, D-IV CA-III, B-I, C-IV, D-II DA-IV, B-II, C-III, D-I

Q20. To make a memory of size 2048 × 8 using chips of size 128 × 4, the number of chips required is:

A8 B16 C32 D64

Q21. Which of the following are sequential circuits?
A. Flip-flop
B. Multiplexer
C. Counter
D. Decoder
E. Adder
Choose the correct answer from the options given below:

AB, D Only BA, C Only CC, E Only DD, A Only

Q22. Techniques for performing I/O:
A. Programmed I/O
B. Interrupt-driven I/O
C. Rotational I/O
D. Direct memory access
E. Channelized I/O
Choose the correct answer from the options given below:

AA and C Only BA, B, and D Only CA, D and E Only DB and E Only

Q23. In 16-bit 2's complement representation, the decimal number −28 is

A1111 1111 0001 1100 B1111 1111 1111 0100 C1111 1111 1110 0100 D1111 1111 1110 0011

Q24. Simplify using a K-map: F(A, B, C, D) = Σm(3, 4, 5, 6, 7, 11, 15)

AAB + C′D BA′B + CD CAC + BD DA′B + B′C

Q25. A 3-bit synchronous counter uses T flip-flops P, Q, R (all clocked together) with inputs T_P = R, T_Q = P′ and T_R = Q′. If the initial state PQR is 000, what are the next three states?

A011, 101, 000 B001, 010, 111 C011, 101, 111 D001, 010, 000