25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.
Correct answer: C. Context Diagram
Correct answer: B. Both A and R are true but R is NOT the correct explanation of A
Correct answer: A. Verifiable
Correct answer: D. Requirement Engineering Process
Correct answer: B. Consistent
Correct answer: A. n1 / n2
Correct answer: C. "Modelling-oriented approach" is one of the methods for specifying functional specifications
Correct answer: B. Requirements elicitation
Correct answer: C. (B) and (D) only
Correct answer: C. 18
Correct answer: B. A-II, B-I, C-III, D-IV
Correct answer: B. entry section, exit section, remainder section
Correct answer: D. Not in deadlock state
Correct answer: A. Producer–Consumer problem
Correct answer: D. wait, signal
Correct answer: A. 0
Correct answer: C. Shared memory segments
Correct answer: C. Yes, P4 P3 P1 P2
Match List I with List II
Correct answer: A. A-IV, B-III, C-I, D-II
In Mano's terminology the address space is the set of virtual addresses, memory space is the set of physical addresses, cache memory uses associative mapping, and a segmented program generates logical addresses.
The write operation in I/O operation does the following-
Correct answer: B. Transfer data from memory to I/O device
An output (write) operation transfers data from memory to the I/O device; a read transfers it from the device to memory.
Which of the following gates do not give output 1 when both the inputs are 0 -
A. NAND gate
B. NOR gate
C. X-OR gate
D. X-NOR gate
Correct answer: D. C Only
With inputs 0, 0: NAND = 1, NOR = 1, XNOR = 1 (inputs equal), XOR = 0. Only XOR fails to output 1.
Which of the following statements are true ?
A. In the write-through policy, only the cache is updated
B. In the write-back policy, both cache and main memory are updated
C. Cache coherence problems exist in multiprocessors with private caches because of the need to share writable data
D. Cache coherence problem can be solved by means of hardware-only scheme
Choose the correct answer from the options given below:
Correct answer: C. C, D Only
Write-through updates cache and memory together (A false); write-back updates only the cache until the block is replaced (B false). Private caches holding shared writable data cause coherence problems (C true), and hardware-only schemes such as snooping solve them (D true).
The right sequence of suboperations that are performed in arithmetic pipeline is-
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Correct answer: A. D, A, B, C
Floating-point add pipeline: compare exponents, align mantissas, add or subtract mantissas, normalize the result: D, A, B, C.
Correct the order of instruction cycle:
A. Read the effective address
B. Fetch the information
C. Execute the instruction
D. Decode the instruction
Correct answer: B. B, D, A, C
Fetch the instruction, decode it, read the effective address, execute: B, D, A, C.