25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.
The following program is stored in the basic computer (locations in hex): 210 CLA; 211 ADD 217; 212 INC; 213 STA 217; 214 LDA 218; 215 CMA; 216 AND 217; 217 1234H; 218 9CE2H. What is the content of the accumulator after execution?
Correct answer: D. 0215H
AC = 0, + 1234 = 1234, INC → 1235, stored at 217. Load 9CE2, complement → 631D. AND with 1235: 631D & 1235 = 0215H.
A non-pipeline system takes to process a task. The same task can be processed in six- segment pipeline with a clockcycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
Correct answer: B. 4.95
Non-pipelined: 500 × 50 ns = 25,000 ns. Pipelined: (6 + 499) × 10 ns = 5050 ns. Speed-up ≈ 4.95.
What is the radix of the numbers if the solutions of x² − 10x + 26 = 0 are x = 4 and x = 7?
Correct answer: D. 11
In base r, '10' = r and '26' = 2r + 6. Sum of roots 4 + 7 = 11 = r, and the product 28 = 2r + 6 also gives r = 11.
Which simplified expressions are correct for F(A, B, C, D) = Σ(0, 1, 2, 3, 6, 12, 13, 14, 15)? (A) A′B′ + AB + A′C′D′ (B) A′B′ + AB + A′CD′ (C) A′B′ + AB + BC′D′ (D) A′B′ + AB + BCD′
Correct answer: D. (B) and (D) only
A′B′ covers 0–3 and AB covers 12–15. Minterm 6 (0110) must be covered by A′CD′ (2, 6) or BCD′ (6, 14). So B and D.
Which of the following statements with respect to K-segment pipelining are true?
(A) Maximum speedup that a pipeline can provide is k theoretically.
(B) It is impossible to achieve maximum speedup k in k-segment pipeline.
(C) All segments in pipeline take same time in computation.
Correct answer: A. (A) and (B) only
A k-stage pipeline's ideal speed-up is k, never reached in practice because of fill time and hazards. Segments generally take different times, so C is false.
Which of the following statements with respect to multiprocessor system are true?
(A) Multiprocessor system is controlled by one operating system.
(B) In Multiprocessor system, multiple computers are connected by the means of communication lines.
(C) Multiprocessor system is classified as multiple instruction stream and multiple data stream system.
Correct answer: C. (A) and (C) only
A multiprocessor runs under one operating system and is an MIMD system. Computers joined by communication lines are a multicomputer/distributed system.
Match List I with List II. List I: A. Handshaking, B. Programmed I/O, C. Interrupt-initiated I/O, D. I/O processor. List II: I. I/O interface informs the CPU that the device is ready for transfer, II. Requires two control signals working in opposite directions, III. Has local memory and controls a large set of I/O devices, IV. Requires the CPU to check the I/O flag and perform the transfer.
Correct answer: C. A-II, B-IV, C-I, D-III
Handshaking uses two control signals in opposite directions; programmed I/O has the CPU polling the flag; with interrupts, the interface tells the CPU it is ready; an IOP has local memory and runs many devices.
Arrange the following types of machine in descending order of complexity.
(A) SISD
(B) MIMD
(C) SIMD
Choose the correct answer from the options given below:
Correct answer: C. B, C, A
MIMD (many instruction and data streams) is the most complex, then SIMD, then SISD.
Given below are two statements:
Statement I : Hardwired control unit can be optimized to produce fast mode of operation.
Statement II : Indirect addressing mode needs two memory reference to fetch the operand. In the light of the above statements, choose the correct answer from the options given below
Correct answer: A. Both Statement I and Statement II are true
Hardwired control is fast because it is built from gates, and indirect addressing reads memory twice (once for the address, once for the operand). Both true.
The Boolean expression AB′ + AB + A′C + AC is unaffected by the value of the Boolean variable
Correct answer: B. B
AB′ + AB = A and A′C + AC = C, so the expression is A + C, which does not depend on B.
A non-pipelined system takes 30 ns to process a task. The same task can be processed in a four- segment pipeline with a clock cycle of 10 ns . Determine the speed up of the pipeline for 100 tasks.
Correct answer: D. 2.91
100 × 30 ns = 3000 ns non-pipelined versus (4 + 99) × 10 = 1030 ns pipelined. Speed-up ≈ 2.91.
A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addresssing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?
Correct answer: C. 1, 4, 8, 19
512K words needs 19 address bits; 256 registers need 8 bits; two addressing modes need 1 bit; the opcode gets the rest: 32 − 19 − 8 − 1 = 4.
A micro instruction format has microoperation field which is divided into 2 subfields F1 and F2, each having 15 distinct microoperations, condition field CD for four status bits, branch field B R having four options used in conjunction AD with address field . The address space is of 128 memory words. The size of micro instruction is :
Correct answer: A. 19
Each of F1 and F2 needs 4 bits (15 operations plus no-op); CD selects 4 conditions (2 bits); BR has 4 options (2 bits); AD addresses 128 words (7 bits). 4 + 4 + 2 + 2 + 7 = 19.
If (142)_b + (112)_(b−2) = (75)_8, find the base b.
Correct answer: D. 5
(75)₈ = 61. (142)_b = b² + 4b + 2 and (112)_(b−2) = (b − 2)² + (b − 2) + 2. Their sum 2b² + b + 6 = 61 gives b = 5.
The following program is stored in the basic computer: 010 CLA; 011 ADD 016; 012 BUN 014; 013 HLT; 014 AND 017; 015 BUN 013; 016 C1A5; 017 93C6. Give the accumulator contents (hex) after execution.
Correct answer: D. 8184
AC = 0, then + C1A5 = C1A5. Jump to 014: AND with 93C6 gives C1A5 & 93C6 = 8184. Jump to 013 and halt.
The Reduced Instruction Set Computer (RISC) characteristics are :
(a) Single cycle instruction execution
(b) Variable length instruction formats
(c) Instructions that manipulates operands in memory
(d) Efficient instruction pipeline
Choose the correct characteristics from the options given below :
Correct answer: C. (a) and (d)
RISC aims for single-cycle execution and efficient pipelining. Variable-length formats and memory-operand instructions are CISC features.
Which of the following binary codes for decimal digits are self complementing?
(a) 8421 code
(b) 2421 code
(c) excess-3 code
(d) excess-3 gray code
Choose the correct option :
Correct answer: B. (b) and (c)
In 2421 and excess-3, the code for 9 − d is the bit complement of the code for d.
An instruction at location 500 has its address field at 501, holding the value 400. Register R1 contains 200. Match each addressing mode with its effective address: (a) Direct, (b) Register indirect, (c) Indexed with R1 as index register, (d) Relative. Values: (i) 200, (ii) 902, (iii) 400, (iv) 600.
Correct answer: A. (a)-(iii), (b)-(i), (c)-(iv), (d)-(ii)
Direct: 400. Register indirect: R1 = 200. Indexed: 400 + 200 = 600. Relative: PC (502 after fetch) + 400 = 902.
Match List I with List II. List I: (a) Isolated I/O, (b) Memory-mapped I/O, (c) I/O interface, (d) Asynchronous data transfer. List II: (i) Same set of control signals for I/O and memory communication, (ii) Separate instructions for I/O and memory communication, (iii) Requires control signals between the communicating units, (iv) Resolves the differences between the central computer and peripherals.
Correct answer: C. (a)-(ii), (b)-(i), (c)-(iv), (d)-(iii)
Isolated I/O has separate I/O instructions; memory-mapped I/O shares memory's control signals; an interface bridges CPU and peripheral differences; asynchronous transfer needs control signals between units.
Match List I with List II. List I: (a) Micro-operation, (b) Microprogrammed control unit, (c) Interrupts, (d) Microinstruction. List II: (i) Specify micro-operations, (ii) Improve CPU utilization, (iii) Control memory, (iv) Elementary operation performed on data stored in registers.
Correct answer: A. (a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)
A micro-operation is an elementary register operation; a microprogrammed control unit uses control memory; interrupts improve CPU utilization; a microinstruction specifies micro-operations.
Which type of addressing mode, less number of memory references are required?
Correct answer: C. Register
In register mode the operand is in a CPU register, so no memory access is needed to fetch it.
Note: Immediate and implied modes also need no memory reference for the operand; the official key is register mode.
Suppose that the register and the register have the bit configuration. Only the three A leftmost bits of are compared with memory K words because has l's in these positions. Because of its organization, this type of memory is uniquely suited to parallel searches by data association. This type of memory is known as
Correct answer: C. content addressable memory
Comparing memory words in parallel against the masked argument register is how content-addressable (associative) memory works.
The fault can be easily diagnosed in the micro- program control unit using diagnostic tools by maintaining the contents of
Correct answer: D. flags, registers and counters
Diagnostic tools inspect the contents of flags, registers and counters of the microprogrammed control unit.
What will be the number of states when a MOD- 2 counter is followed by a MOD- 5 counter?
Correct answer: B. 10
Cascading MOD-2 and MOD-5 gives a MOD-10 counter (2 × 5 states).
The parallel bus arbitration technique uses an external priority encoder and a decoder. Suppose, a parallel arbiter has 5 bus arbiters. What will be the size of the priority encoder and decoder respectively?
Correct answer: D. 8 × 3, 3 × 8
5 arbiters need 3 bits, so an 8 × 3 priority encoder and a 3 × 8 decoder.
