25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.
Match List I with List II. List I: A. (100110011)₂, B. Complements, C. Parity bits, D. Variable-length instruction. List II: I. Error detection code; II. CISC; III. Negative number; IV. (133)₁₆.
Correct answer: B. A-IV, B-III, C-I, D-II
Grouping 1 0011 0011 in fours gives hex 133. Complements represent negative numbers; parity bits detect errors; variable-length instructions are typical of CISC.
Which of the following are not data manipulation instructions? A. Call B. Load C. And D. Increment E. Shift
Correct answer: B. A & B only
AND, increment and shift manipulate data (logical, arithmetic, shift). CALL is a program-control instruction and LOAD is a data-transfer instruction.
Which of the following do not represent memory-reference instructions? A. mode = 1, opcode = 010 B. mode = 0, opcode = 111 C. mode = 1, opcode = 111 D. mode = 1, opcode = 110 E. mode = 1, opcode = 001
Correct answer: A. B & C only
In Mano's basic computer, opcodes 000–110 are memory-reference instructions (mode bit chooses direct or indirect). Opcode 111 is a register-reference instruction when I = 0 and an I/O instruction when I = 1. So B and C are not memory-reference.
Consider the number (45)ᵧ, where y is the base. Some possible values of y are: (A) 5 (B) 6 (C) 7 (D) 8
Correct answer: B. (B), (C) and (D) Only
A base-y numeral can only use digits 0 to y−1. The digit 5 needs y ≥ 6, so 6, 7 and 8 are possible but 5 is not.
Find the correct sequence of the storage devices in descending order based on their access time.
(A) Registers
(B) Magnetic Disk
(C) Magnetic Tapes
(D) Main memory
(E) Optical Disk
Correct answer: D. (C), (E), (B), (D), (A)
Slowest to fastest: magnetic tape, optical disk, magnetic disk, main memory, registers.
Match List - I with List - II.
Correct answer: C. (A)-(IV), (B)-(I), (C)-(II), (D)-(III)
A half adder adds two bits; a decoder has n inputs and 2ⁿ outputs; a register is a CPU storage unit; main memory stores the program at run time.
Consider the following statements regarding combinational and sequential circuits.
(A) Output of combinational circuits depends on the only current input.
(B) Output of combinational circuit depends on the both current input and previous output.
(C) Output of sequential circuit depends on the current input.
(D) Output of sequential circuit depends on both current input and previous output.
Correct answer: B. (A) and (D) Only
Combinational outputs depend only on the current inputs; sequential outputs depend on the current inputs and the stored state (previous outputs).
Correct answer: C. (A)-(II), (B)-(I), (C)-(IV), (D)-(III)
An N-bit ring counter cycles through exactly N states; a synchronous counter clocks all flip-flops together; an asynchronous (ripple) counter applies the clock only to the first flip-flop; a decade counter counts 0 to 9.
Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order.
(A) Initiate DMA transfer request
(B) Transfer data directly between peripheral and memory
(C) Processor grants DMA control over the system bus
(D) DMA controller completes data transfer and signals completion
Correct answer: B. (A),(C),(B),(D)
The device or controller requests DMA, the processor grants control of the bus, data moves directly between device and memory, and the controller signals completion (interrupt).
The instruction LD ADR (X) which is equivalent to ← AC M[ADR+XR] is in :
Correct answer: C. Index Addressing Mode
AC ← M[ADR + XR] adds the index register to the address field, which is indexed addressing.
Match the List-I and List-II
Correct answer: C. A-III, B-I, C-IV, D-II
Complements represent negative numbers; XOR gates form adders; the accumulator holds ALU results; the control unit decodes instructions.
For making a memory of size 2048 x 8 bytes, by using the chips of size 128 x 4 bytes, the number of chips required is :
Correct answer: C. 32
Chips needed = (2048 × 8) ÷ (128 × 4) = 16 × 2 = 32: 16 rows to cover the words, 2 chips side by side for the width.
Which of the following are sequential circuits?
A. Flip flop
B. Multiplexer
C. Counter
D. Decoder
E. Adder
Correct answer: B. A, C Only
Flip-flops and counters store state, so they are sequential. Multiplexers, decoders and adders are combinational.
Techniques for performing I/O :
A. Programmed I/O
B. Interrupt-driven I/O
C. Rotational I/O
D. Direct memory access
E. Channelized I/O
Correct answer: B. A, B, and D Only
The three I/O techniques are programmed I/O, interrupt-driven I/O and direct memory access.
The interface(s) that provide(s) I/0 transfer of data directly to and from the memory unit peripheral is/are termed as:
(A) DMA (Direct Memory Access)
(B) IOP (Input-Output Processor)
(C) Serial Interface
(D) Parallel Interface
Correct answer: C. (A) and (B) Only
Both a DMA controller and an I/O processor transfer data directly between peripherals and memory without the CPU moving each word.
Which of the following(s) are main memory?
(A) Virtual memory
(B) Cache memory
(C) RAM
(D) SSD
Correct answer: B. (B) and (C) Only
RAM is main (primary) memory and the official key also includes cache. Virtual memory is an abstraction backed by disk, and an SSD is secondary storage.
Note: Strictly, main memory is RAM; cache is a separate, faster level of primary memory. The official key counts cache as well.
List - I List - II
(a) SZA (I) Increment M and skip it zero
(b) SKI (II) Skip if AC is negative
(c) SNA (III) Skip if input flag is on
(d) ISZ (IV) Skip if AC is Zero
Correct answer: B. (a)-(IV), (b)-(III), (c)-(II), (d)-(I)
In Mano's basic computer: SZA skips if AC is zero; SKI skips if the input flag is on; SNA skips if AC is negative; ISZ increments M and skips if zero.
In most general case, the computer needs to process each instruction with the following sequence of steps:
(A) Calculate the effective address
(B) Execute the instruction
(C) Fetch the instruction from memory
(D) Fetch the operand from memory
(E) Decode the instruction
Correct answer: B. (C),(E),(A),(D),(B)
Fetch the instruction, decode it, calculate the effective address, fetch the operand, execute.
What is the 4+4 bit binary fixed-point equivalent of −(3.72)₁₀?
Correct answer: C. 1100.0100
3.72: integer part 0011; 0.72 × 16 = 11.52 ≈ 12 = 1100, so 3.72 ≈ 0011.1100. Two's complement: invert to 1100.0011 and add 1 → 1100.0100.
Let ⊕ denote XOR, and 1 and 0 the binary constants. F(P, Q) = ((1 ⊕ P) ⊕ (P ⊕ Q)) ⊕ ((P ⊕ Q) ⊕ (Q ⊕ 0)). Which of the following is equivalent to F?
Correct answer: D. (P ⊕ Q)′
(1 ⊕ P) ⊕ (P ⊕ Q) = 1 ⊕ Q, since P ⊕ P = 0. (P ⊕ Q) ⊕ (Q ⊕ 0) = P. So F = 1 ⊕ Q ⊕ P = (P ⊕ Q)′, i.e. XNOR.
A processor chip is used for application in which 30 % of execution time is spent on floating point addition. For the new model of the processor, the design team has come up with redesign the floating point adder to make it twice as fast. What will be possible maximum speed up by this redesign?
Correct answer: C. 1.18
Speed-up = 1 / (0.7 + 0.3/2) = 1 / 0.85 ≈ 1.18.
256 Mb DRAM is organized as a 16 K × 16 K memory externally and as a square array internally. Each row must be refreshed at least once every 50 mili second to forestall loss of data; refreshing one row takes 100 nanoseconds. What fraction of the total memory bandwidth is lost to refresh cycles?
Correct answer: B. 3.3%
16K rows × 100 ns = 1.6384 ms of refresh in every 50 ms. Fraction = 1.6384 / 50 ≈ 3.3%.
In 16-bit 2's Complementation representation, the decimal number 28 is
Correct answer: C. 1111 1111 1110 0100
28 = 0000 0000 0001 1100. Inverting gives 1111 1111 1110 0011, and adding 1 gives 1111 1111 1110 0100, which is −28.
Note: The key corresponds to −28; the minus sign appears to be missing from the question. +28 is 0000 0000 0001 1100.
Simplify using a K-map: F(A, B, C, D) = Σ(3, 4, 5, 6, 7, 11, 15)
Correct answer: B. A′B + CD
Minterms 4, 5, 6, 7 form the quad A′B. Minterms 3, 7, 11, 15 form the quad CD. So F = A′B + CD.
Consider a 3-bit counter designed using T flip-flops as shown (Tp = R, Tq = P′, Tr = Q′, all clocked together). If the initial state PQR is 000, what are the next three states?
Correct answer: A. 011, 101, 000
From the circuit, Tp = R, Tq = P′ and Tr = Q′; a T flip-flop toggles when T = 1. 000: Tp = 0, Tq = 1, Tr = 1 → 011. 011: Tp = 1, Tq = 1, Tr = 0 → 101. 101: Tp = 1, Tq = 0, Tr = 1 → 000.
