Paper 2 CS · UNIT 02 · MOCK TEST

Computer System Architecture — Mock Test 2

25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.

0 / 25 answered 00:00

Q1. Which of the following is the simplified form of the function f(A, B, C) = Σm(0, 1, 3, 7)?

AA′B′C′ + A′B′C + A′BC + ABC BA′B′ + A′BC + ABC CA′B′ + BC DA′B′ + BC′

Q2. Which table for a dynamic pipeline becomes more interesting when a nonlinear pattern is followed?

AReservation Table BConfusion Table CInverted Table DGreedy Table

Q3. Arrange the instruction cycle in the correct order:
A. Read the effective address
B. Fetch the instruction
C. Execute the instruction
D. Decode the instruction
Choose the correct answer from the options given below:

AA, B, C, D BB, D, A, C CB, A, D, C DA, B, D, C

Q4. Which of the following is the complement of the Boolean function A′B + CD′ + A′B + CD′?

AA′B + CD′ B(A′ + B)(C + D′) C(A + B′)(C′ + D) DAB′ + CD′

Q5. Which of the following is the correct sequence with regard to the interrupt service routine?
A. Save contents of processor registers
B. Turn the interrupt facility on
C. Service the device whose flag is set
D. Check which flag is set
E. Restore contents of processor registers
Choose the correct answer from the options given below:

AA, B, C, D, E BD, B, C, A, E CD, C, B, E, A DA, D, C, E, B

Q6. Match List I (Boolean Algebra Law) with List II (Axioms)

List I	List II
A. Absorption Law	I. a + 1 = 1
B. Bounded Law	II. a + 0 = a
C. Identity Law	III. a·(b + c) = (a·b) + (a·c)
D. Distributive Law	IV. a + (a·b) = a

AA-IV, B-I, C-II, D-III BA-IV, B-III, C-I, D-II CA-III, B-IV, C-II, D-I DA-II, B-III, C-IV, D-I

Q7. Match List I with List II

List I	List II
A. (100110011)₂	I. Error detection code
B. Complements	II. CISC
C. Parity Bits	III. Negative number
D. Variable length instruction	IV. (133)₁₆

AA-IV, B-I, C-III, D-II BA-IV, B-III, C-I, D-II CA-IV, B-II, C-III, D-I DA-I, B-IV, C-II, D-III

Q8. Which of the following are NOT data manipulation instructions?
A. Call
B. Load
C. And
D. Increment
E. Shift
Choose the correct answer from the options given below:

AC & E only BA & B only CD & E only DA & C only

Q9. In the basic computer instruction format [I | opcode | address], which of the following do NOT represent memory-reference instructions?
A. mode = 1, opcode = 010
B. mode = 0, opcode = 111
C. mode = 1, opcode = 111
D. mode = 1, opcode = 110
E. mode = 1, opcode = 001
Choose the correct answer from the options given below:

AB & C only BB & D only CA & D only DA & E only

Q10. Consider the number (45)ᵧ where y is the base of the number. Some of the possible values of y are given below.
(A) 5
(B) 6
(C) 7
(D) 8
Choose the correct answer from the options given below:

A(A), (B) and (C) Only B(B), (C) and (D) Only C(A), (C) and (D) Only D(A), (B), (C) and (D)

Q11. Find the correct sequence of the storage devices in descending order based on their access time.
(A) Registers
(B) Magnetic Disk
(C) Magnetic Tapes
(D) Main memory
(E) Optical Disk
Choose the correct answer from the options given below:

A(B), (A), (D), (C), (E) B(B), (A), (E), (D), (C) C(C), (B), (A), (E), (D) D(C), (E), (B), (D), (A)

Q12. A CPU has a 5-stage pipeline with stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions?

A10 B14 C15 D19

Q13. Match List I (computing systems) with List II (working/output)

List I	List II
(A) Half Adder	(I) Has n inputs and 2ⁿ outputs
(B) Decoder	(II) CPU storage unit
(C) Register	(III) Used to store program at runtime
(D) Main memory	(IV) 2-bit addition circuit

A(A)-(II), (B)-(III), (C)-(IV), (D)-(I) B(A)-(IV), (B)-(II), (C)-(III), (D)-(I) C(A)-(IV), (B)-(I), (C)-(II), (D)-(III) D(A)-(II), (B)-(IV), (C)-(III), (D)-(I)

Q14. Consider the following statements regarding combinational and sequential circuits.
(A) The output of a combinational circuit depends only on the current input.
(B) The output of a combinational circuit depends on both the current input and the previous output.
(C) The output of a sequential circuit depends only on the current input.
(D) The output of a sequential circuit depends on both the current input and the previous output (state).
Choose the correct answer from the options given below:

A(A) and (C) Only B(A) and (D) Only C(B) and (D) Only D(B) and (C) Only

Q15. Arrange the following steps in the proper sequence for simplifying a Boolean function using a Karnaugh map (K-map).
(A) Identify and group the largest possible clusters of 1's
(B) Draw the K-map for the given Boolean function
(C) Write the simplified Boolean expression from the grouped clusters
(D) Transfer the truth table values to the K-map
Choose the correct answer from the options given below:

A(B), (D), (A), (C) B(D), (B), (A), (C) C(B), (A), (D), (C) D(A), (B), (C), (D)

Q16. Match List I (Counter) with List II (uses/working)

List I	List II
(A) N-bit Ring Counter	(I) Uses universal clock
(B) Synchronous Counter	(II) Counts exactly N states
(C) Asynchronous Counter	(III) Counts 0 to 9
(D) Decimal Counter	(IV) Main clock is applied to the first flip-flop only

A(A)-(II), (B)-(IV), (C)-(I), (D)-(III) B(A)-(IV), (B)-(II), (C)-(III), (D)-(I) C(A)-(II), (B)-(I), (C)-(IV), (D)-(III) D(A)-(IV), (B)-(I), (C)-(II), (D)-(III)

Q17. Consider the following statements regarding special-purpose registers.
(A) The Program Counter (PC) keeps track of the next instruction to be executed.
(B) The Instruction Register holds the address of the first instruction to be executed.
(C) The Accumulator holds the output of the ALU.
(D) The Program Counter (PC) keeps track of only the first instruction of the program.
Choose the correct answer from the options given below:

A(A) and (C) Only B(A) and (D) Only C(B) and (D) Only D(A), (B) and (C) Only

Q18. A multiprocessor system with 16 processors is used to execute a parallelizable task. The serial portion of the task takes 200 clock cycles and the parallel portion takes 800 clock cycles. When all 16 processors are used, how many total clock cycles are required to complete the task?

A250 B300 C400 D450

Q19. Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order.
(A) Initiate DMA transfer request
(B) Transfer data directly between peripheral and memory
(C) Processor grants DMA control over the system bus
(D) DMA controller completes data transfer and signals completion
Choose the correct answer from the options given below:

A(C), (A), (B), (D) B(A), (C), (B), (D) C(A), (B), (C), (D) D(C), (B), (A), (D)

Q20. A vector processor with 16 lanes can perform an operation on 1024 elements, with each operation taking 5 clock cycles (pipelined). How many cycles are needed to complete the operation?

A64 B80 C100 D128

Q21. Which of the following circuits is used to store one bit of data?

AEncoder BDecoder CFlip-Flop DRegister

Q22. Identify the code sequence: 1010, 1011, 1001, 1000

ABCD BExcess-3 CGray DExcess-3 Gray

Q23. The microoperation which divides a signed binary number by 2 is:

ACircular shift BLogical shift CArithmetic shift right DArithmetic shift left

Q24. A program that is used by other routines to accomplish a particular task is called:

AMicro program BMicro operation CRoutine DSubroutine

Q25. A system bus in which each data item is transferred during a time slice known in advance to both the source and destination units is called:

AMIMD BDMA CAsynchronous bus DSynchronous bus