25 questions · about 30 minutes. Press End Mock any time to see your score and the correct answers.
Consider F = (X + Y + Z)(X′ + Y)(Y′ + Z). Which of the following are equivalent to F′? A. (X′ + Y′ + Z′)(X + Y′)(Y + Z′) B. XY′ + Z′ C. (X + Z′)(Y′ + Z′) D. XY′ + YZ′ + X′Y′Z′
Correct answer: B. B, C and D Only
By De Morgan, F′ = X′Y′Z′ + XY′ + YZ′ (D). This simplifies: YZ′ + X′Y′Z′ + XY′Z′ = Z′, so F′ = XY′ + Z′ (B). Expanding (X + Z′)(Y′ + Z′) also gives XY′ + Z′ (C). Expression A is not equal.
Which of the following statement is/are True?
A. The processor has direct access to both primary and secondary memory
B. Primary memory stores the active instructions and data for the program being executed on the process
C. Secondary memory is used as a backup memory
D. Memory system is implemented on a single level memory
Correct answer: B. B and C only
Primary memory holds the active program and data (B), and secondary memory serves as backup storage (C). The CPU cannot access secondary memory directly (A false), and real memory systems are multi-level (D false).
Match List I with List II
Correct answer: B. A-IV, B-III, C-II, D-I
DAA (decimal adjust) is arithmetic; LXI (load register pair immediate) is data movement; RST (restart) is an interrupt instruction; JMP is program control.
The sequence of events that happen during a typical fetch operation is/are:
A. Memory
B. MBR
C. MAR
D. PC
E. IR
Choose the correct order from the options given below:
Correct answer: B. D, C, A, B, E
PC → MAR, memory is read, the word goes into the MBR, then to the IR: D, C, A, B, E.
The memory size for n address lines and m data lines is given by
Correct answer: C. 2ⁿ × m
n address lines select 2ⁿ locations, each m bits wide: 2ⁿ × m bits.
Simplify using a K-map: F(A, B, C, D) = Σ(0, 2, 5, 7, 8, 10, 13, 15)
Correct answer: A. BD + B′D′
Minterms 0, 2, 8, 10 are the four corners: B′D′. Minterms 5, 7, 13, 15 form the centre quad: BD. F = BD + B′D′.
Consider an unpipelined machine with 10 nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: 40 %, 20 % and 40 %, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered?
Correct answer: B. 4 times
Unpipelined average = 10 ns × (0.4×4 + 0.2×4 + 0.4×5) = 44 ns. The pipelined machine completes one instruction per 11 ns clock (10 + 1 overhead). Speed-up = 44/11 = 4.
Which of the following statement is/are false? 1. The processor has direct access to both primary and secondary memory 2. Primary memory stores the active instructions and data for the program being executed on the Q process 3. Secondary memory is used as a backup memory 4. Memory system is implemented on a single- level memory
Correct answer: D. 1 and 4 only
The CPU accesses primary memory directly but not secondary memory (1 false), and memory is organized as a multi-level hierarchy (4 false). Statements 2 and 3 are true.
Match List-I and List-II
Correct answer: C. a-III, b-IV, c-II, d-I
STA FFFFH uses a direct address; MOV A, M uses the address in HL (indirect); MOV A, B is register addressing; MVI A, FFH is immediate.
The correct sequence in the fetch-execute cycle is _______ .
I. Decode
II. Fetch
III. Execute Chose the correct answer from the following
Correct answer: D. II-I-III
Fetch, then decode, then execute.
Consider a memory system with addresses spaced at a distance m, bank cycle time T and n banks. The average data access time per word in synchronous organization is
Correct answer: A. t = m·T/n for m << n; T for m >> n
With stride m, successive accesses fall in banks m apart, so only about n/m banks work in parallel: t ≈ m·T/n when m is much smaller than n. When m ≥ n, every access hits the same bank and must wait a full cycle T.
For a multiprocessor system, an interconnection network such as a crossbar switch is an example of
Correct answer: A. Non-blocking network
A crossbar has a switch at every input–output crossing, so any free input can reach any free output without blocking: it is a non-blocking network.
A 4-stage pipeline has stage delays of 150, 120, 160 and 140 ns. The registers between stages have a delay of 5 ns. Assuming a constant clocking rate, the total time required to process 1000 data items on this pipeline is
Correct answer: B. 165.5 ms
Clock period = slowest stage + latch delay = 160 + 5 = 165 ns. Time for 1000 items = (4 + 999) × 165 ns ≈ 165.5 μs.
Note: The computed time is 165.5 μs; the options say ms.
Match List I with List II. List I: (A) Stack overflow, (B) Timer, (C) Invalid opcode, (D) Supervisor call. List II: (I) Software interrupt, (II) Internal interrupt, (III) External interrupt, (IV) Machine check interrupt.
Correct answer: D. (A)-(II), (B)-(III), (C)-(IV), (D)-(I)
Stack overflow is an internal interrupt (trap); a timer is external; an invalid opcode raises a machine-check style exception (per the key); a supervisor call is a software interrupt.
Statement I: Consider the 20-bit 'Branch' microinstruction format: F1 (3 bits), F2 (3), F3 (3), CD (2), BR (2), AD (7), where F1–F3 are micro-operation fields, CD is the branch condition, BR the branch field and AD the address field. Statement II: An instruction in this format can perform a branch in 4 conditions.
Correct answer: A. Both Statement I and Statement II are correct
The 20-bit format 3 + 3 + 3 + 2 + 2 + 7 is Mano's microinstruction format (Statement I correct). The 2-bit CD field selects one of 2² = 4 branch conditions (Statement II correct).
Match List I with List II. List I: A. Odd function, B. Universal gate, C. 2421 code, D. Buffer. List II: I. NAND gate, II. XOR gate, III. Amplification, IV. Self-complementing.
Correct answer: B. A ‐ II, B ‐ I, C ‐ IV, D ‐ III
XOR is the odd function; NAND is a universal gate; 2421 is a self-complementing code; a buffer amplifies (drives) a signal.
The octal equivalent of (D.C)₁₆ is
Correct answer: A. (15.6)₈
D.C = 1101.1100 in binary. Group in threes from the point: 001 101 . 110 = 15.6 in octal.
A digital computer has a common bus system for 8 registers 16 bits each. How many multiplexers are required to implement common bus? What size of multiplexers is required?
Correct answer: A. 16, 8 × 1
One multiplexer per bit of the bus (16), each selecting among the 8 registers (8 × 1).
Which of the following is not an example of pseudo‐instruction?
Correct answer: D. HLT
ORG, DEC and END are assembler directives (pseudo-instructions). HLT is a real machine instruction.
Arrange the following in the increasing order of complexity.
A. I/O Module
B. I/O processor
C. I/O Channel
D. DMA
Correct answer: D. A, D, C, B
Complexity increases from a simple I/O module, to a DMA controller, to an I/O channel, to a full I/O processor.
The characteristics of the combinational circuits are:
A. Output at any time is function of inputs at that time
B. Contains memory elements
C. Do not have feedback paths
D. Clock is used to trigger the circuits to obtain outputs
Correct answer: C. A and C only
Combinational outputs depend only on current inputs and there are no feedback paths. Memory and clocks belong to sequential circuits.
The cache coherence problem can be solved
A. by having multiport memory
B. allow only nonshared data to be stored in cache
C. using a snoopy cache controller
D. using memory interleaving
Coherence can be ensured by caching only non-shared data or by snoopy cache controllers. Multiport memory and interleaving do not address coherence.
Given below are two statements
Statement I: CISC computers have a large of number of addressing modes.
Statement II: In RISC machines memory access is limited to load and store instructions. In light of the above statements, choose the correct answer from the options given below
Correct answer: A. Both Statement I and Statement II are true
CISC machines have many addressing modes, and RISC machines access memory only through load and store instructions. Both true.
Which of the following statements is true?
Correct answer: B. Program control instructions are used to alter the sequential flow of the program.
Program-control instructions (branch, jump, call) change the sequential flow. Control memory belongs to microprogrammed control, register-indirect differs from displacement, and interrupts do affect CPU utilization.
A machine has a byte-addressable main memory of 2¹⁶ bytes and a block size of 8 bytes. A direct-mapped cache with 32 lines is used. How many bits are in the tag, line and word fields of the address?
Correct answer: A. 8, 5, 3
Word = log₂ 8 = 3 bits; line = log₂ 32 = 5 bits; tag = 16 − 5 − 3 = 8 bits.
