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Paper 2 CS · UNIT 02

Computer System Architecture – Previous Year Questions

224 questions from past UGC NET Paper 2 – Computer Science papers, each with the correct answer. Open any question for its explanation.

  1. Which of the following ICs has lowest power consumption?
    Answer: D. CMOS Paper 2 CS · 22 June 2026
  2. Consider the following binary codes:C₁ 00000 C₂ 01011 C₃ 10101 What is the maximum Hamming Distance value for all pairs of above mentioned codes?
    Answer: C. 4 Paper 2 CS · 22 June 2026
  3. The average memory access time is 130 ns and average time of cache memory is 100 ns. With 75% hit ratio, the average time to access a word is?
    Answer: C. 132.5 ns Paper 2 CS · 22 June 2026
  4. Simplify the following Boolean expression using 4-variables K-map. F(A, B, C, D) = Σ m(3, 6, 7, 11, 12, 13, 14, 15)
    Answer: C. AB + BC + CD Paper 2 CS · 22 June 2026
  5. Which of the following is memory interleaving?
    Answer: C. Division of memory into multiple modules, allowing the CPU to access multiple m… Paper 2 CS · 22 June 2026
  6. Arrange the following in terms of their capacity from smallest to largest: A. L3 Cache B. L1 Cache C. CPU Register D. L2 Cache Choose the correct answer from the options given below:
    Answer: C. C, B, D, A Paper 2 CS · 22 June 2026
  7. The combination of selection lines for sending the input I14 to output in the following multiplexer is? (A 64×1 MUX with inputs I0...I63 and selection lines S5, S4, S3, S2, S1, S0 is shown, driving a single output.)
    Answer: D. 001110 Paper 2 CS · 22 June 2026
  8. Match the LIST-I with LIST-IILIST-I LIST-II A. FDM I. has four possible Minterms B. Digital Circuits II. Frequency Division Multiplexing C. A Two-Variable function III. Universal flip-flop D. J-K flip-flop IV. Combinati…
    Answer: B. A-II, B-IV, C-I, D-III Paper 2 CS · 22 June 2026
  9. For sending input I6 on the output line of a 8×1 multiplexer, (an 8×1 MUX with inputs I0...I7, selection lines S2, S1, S0, driving output O/P, is shown) which of the following will represent the combination of selection…
    Answer: C. 110 Paper 2 CS · 22 June 2026
  10. The term "double buffered" is used in which of the following?
    Answer: B. Asynchronous Communication Interface Paper 2 CS · 22 June 2026
  11. What does "Amdahl's Law" describe in the context of parallel processing?
    Answer: A. Maximum speedup achievable, considering serial and parallel portions of a progr… Paper 2 CS · 22 June 2026
  12. The transformation of data from main memory to cache memory is referred as:
    Answer: C. Mapping Paper 2 CS · June 2025
  13. Consider the Boolean expression A(x, y, z) = x(y′z)′. Which of the following is the complete sum-of-products form of the given Boolean expression?
    Answer: D. xyz + xyz′ + xy′z′ Paper 2 CS · June 2025
  14. Match List I with List IIList I List II A. Address Space I. Associative Mapping B. Memory Space II. Logical address C. Cache Memory III. Physical address D. Segmented Program IV. Virtual address
    Answer: A. A-IV, B-III, C-I, D-II Paper 2 CS · June 2025
  15. Binary equivalent to (A0F)16 is:
    Answer: C. 101000001111 Paper 2 CS · June 2025
  16. Gray code equivalent to decimal number 8 is:
    Answer: B. 1100 Paper 2 CS · June 2025
  17. The write operation in an I/O operation does the following
    Answer: B. Transfer data from memory to I/O device Paper 2 CS · June 2025
  18. Which of the following gates do NOT give output 1 when both the inputs are 0? A. NAND gate B. NOR gate C. X-OR gate D. X-NOR gate Choose the correct answer from the options given below:
    Answer: D. C Only Paper 2 CS · June 2025
  19. The computer needs to process each instruction with the following sequence of steps: A. Calculate the effective address B. Fetch the instruction from memory C. Decode the instruction D. Fetch the operands from the memor…
    Answer: C. B, C, A, D, E Paper 2 CS · June 2025
  20. Which of the following statements are true? A. In the write-through policy, only the cache is updated B. In the write-back policy, both cache and main memory are updated C. Cache coherence problems exist in multiprocess…
    Answer: C. C, D Only Paper 2 CS · June 2025
  21. The right sequence of a CPU program to input data will be: A. Read status register B. Check flag bit C. Read data register D. Transfer data to memory Choose the correct answer from the options given below:
    Answer: A. A, B, C, D Paper 2 CS · June 2025
  22. The right sequence of suboperations that are performed in an arithmetic pipeline (floating-point addition) is A. Align the mantissas B. Add or subtract the mantissas C. Normalize the result D. Compare the exponents Choo…
    Answer: A. D, A, B, C Paper 2 CS · June 2025
  23. Consider a pipeline unit for fixed-point multiplication of 8-bit integers. Arrange the following stages in the correct sequence. Stage A: Consists of two CSAs and it merges four numbers from the previous stage. Stage B:…
    Answer: B. D, C, A, B Paper 2 CS · December 2024
  24. Which are often needed to evaluate the cache performance?
    Answer: A. Hit Ratio Paper 2 CS · December 2024
  25. Arrange the following in increasing order with respect to access time. A. Solid State Drive B. Optical Disks C. DRAMs D. SRAMs E. Registers Choose the correct answer from the options given below:
    Answer: D. E, D, C, A, B Paper 2 CS · December 2024
  26. Which of the following is the simplified form of the function f(A, B, C) = Σm(0, 1, 3, 7)?
    Answer: C. A′B′ + BC Paper 2 CS · December 2024
  27. Which table for a dynamic pipeline becomes more interesting when a nonlinear pattern is followed?
    Answer: A. Reservation Table Paper 2 CS · December 2024
  28. Arrange the instruction cycle in the correct order: A. Read the effective address B. Fetch the instruction C. Execute the instruction D. Decode the instruction Choose the correct answer from the options given below:
    Answer: B. B, D, A, C Paper 2 CS · December 2024
  29. Which of the following is the complement of the Boolean function A′B + CD′ + A′B + CD′?
    Answer: C. (A + B′)(C′ + D) Paper 2 CS · December 2024
  30. Which of the following is the correct sequence with regard to the interrupt service routine? A. Save contents of processor registers B. Turn the interrupt facility on C. Service the device whose flag is set D. Check whi…
    Answer: D. A, D, C, E, B Paper 2 CS · December 2024