Computer System Architecture – Previous Year Questions
224 questions from past UGC NET Paper 2 – Computer Science papers, each with the correct answer. Open any question for its explanation.
- Consider F = (X + Y + Z)(X′ + Y)(Y′ + Z). Which of the following are equivalent to F′? A. (X′ + Y′ + Z′)(X + Y′)(Y + Z′) B. XY′ + Z′ C. (X + Z′)(Y′ + Z′) D. XY′ + YZ′ + X′Y′Z′
- Which of the following statement is/are True? A. The processor has direct access to both primary and secondary memory B. Primary memory stores the active instructions and data for the program being executed on the proce…
- Match List I with List II
- The sequence of events that happen during a typical fetch operation is/are: A. Memory B. MBR C. MAR D. PC E. IR Choose the correct order from the options given below:
- The memory size for n address lines and m data lines is given by
- Simplify using a K-map: F(A, B, C, D) = Σ(0, 2, 5, 7, 8, 10, 13, 15)
- Consider an unpipelined machine with 10 nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: 4…
- Which of the following statement is/are false? 1. The processor has direct access to both primary and secondary memory 2. Primary memory stores the active instructions and data for the program being executed on the Q pr…
- Match List-I and List-II
- The correct sequence in the fetch-execute cycle is _______ . I. Decode II. Fetch III. Execute Chose the correct answer from the following
- Consider a memory system with addresses spaced at a distance m, bank cycle time T and n banks. The average data access time per word in synchronous organization is
- For a multiprocessor system, an interconnection network such as a crossbar switch is an example of
- A 4-stage pipeline has stage delays of 150, 120, 160 and 140 ns. The registers between stages have a delay of 5 ns. Assuming a constant clocking rate, the total time required to process 1000 data items on this pipeline…
- Match List I with List II. List I: (A) Stack overflow, (B) Timer, (C) Invalid opcode, (D) Supervisor call. List II: (I) Software interrupt, (II) Internal interrupt, (III) External interrupt, (IV) Machine check interrupt.
- Statement I: Consider the 20-bit 'Branch' microinstruction format: F1 (3 bits), F2 (3), F3 (3), CD (2), BR (2), AD (7), where F1–F3 are micro-operation fields, CD is the branch condition, BR the branch field and AD the…
- Match List I with List II. List I: A. Odd function, B. Universal gate, C. 2421 code, D. Buffer. List II: I. NAND gate, II. XOR gate, III. Amplification, IV. Self-complementing.
- The octal equivalent of (D.C)₁₆ is
- A digital computer has a common bus system for 8 registers 16 bits each. How many multiplexers are required to implement common bus? What size of multiplexers is required?
- Which of the following is not an example of pseudo‐instruction?
- Arrange the following in the increasing order of complexity. A. I/O Module B. I/O processor C. I/O Channel D. DMA
- The characteristics of the combinational circuits are: A. Output at any time is function of inputs at that time B. Contains memory elements C. Do not have feedback paths D. Clock is used to trigger the circuits to obtai…
- The cache coherence problem can be solved A. by having multiport memory B. allow only nonshared data to be stored in cache C. using a snoopy cache controller D. using memory interleaving
- Given below are two statements Statement I: CISC computers have a large of number of addressing modes. Statement II: In RISC machines memory access is limited to load and store instructions. In light of the above statem…
- Which of the following statements is true?
- A machine has a byte-addressable main memory of 2¹⁶ bytes and a block size of 8 bytes. A direct-mapped cache with 32 lines is used. How many bits are in the tag, line and word fields of the address?
- The following program is stored in the basic computer (locations in hex): 210 CLA; 211 ADD 217; 212 INC; 213 STA 217; 214 LDA 218; 215 CMA; 216 AND 217; 217 1234H; 218 9CE2H. What is the content of the accumulator after…
- A non-pipeline system takes to process a task. The same task can be processed in six- segment pipeline with a clockcycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
- What is the radix of the numbers if the solutions of x² − 10x + 26 = 0 are x = 4 and x = 7?
- Which simplified expressions are correct for F(A, B, C, D) = Σ(0, 1, 2, 3, 6, 12, 13, 14, 15)? (A) A′B′ + AB + A′C′D′ (B) A′B′ + AB + A′CD′ (C) A′B′ + AB + BC′D′ (D) A′B′ + AB + BCD′
- Which of the following statements with respect to K-segment pipelining are true? (A) Maximum speedup that a pipeline can provide is k theoretically. (B) It is impossible to achieve maximum speedup k in k-segment pipelin…