Computer System Architecture – Previous Year Questions
224 questions from past UGC NET Paper 2 – Computer Science papers, each with the correct answer. Open any question for its explanation.
- The instruction LD ADR(X), equivalent to AC ← M[ADR + XR], is in:
- The instructions ADD R1, A, B ADD R2, C, D MUL X, R1, R2 evaluate X = (A + B) * (C + D) using which of the following?
- The Boolean expression for F(A, B, C) = Σm(0, 2, 6) with don't-cares d(A, B, C) = Σ(1, 3, 5) would be:
- A computer system has a cache access time of 100 ns, a main-memory access time of 1100 ns and a hit ratio of 0.9. The average access time would be:
- Match List I (Boolean expression) with List II (dual of the Boolean expression)List I List II A. x·y + 0 I. (x̄ + 0)·(ȳ·z) B. x̄·1 + (ȳ + z) II. (x + y)·1 C. x̄·(ȳ + 0) III. x̄ + ȳ·1 D. x·1 + (y + z̄) IV. (x + 0)·(y·z̄)
- The I/O method in which memory addresses and I/O addresses are distinct is called A. Isolated I/O B. Memory-mapped I/O C. Strobe control D. Handshaking E. Interrupt Choose the most appropriate answer from the options gi…
- Arrange the following from fastest to slowest: A. DRAM B. SRAM C. CPU registers D. Magnetic tapes E. Hard disk Choose the correct answer from the options given below:
- Regarding the interrupt service subroutine, consider the following tasks: A. Turn the interrupt facility on B. Service the device whose flag is set C. Save the contents of processor registers D. Check which flag is set…
- Match List I with List IIList I List II A. Complement I. Adder B. E-OR II. Instruction decoding C. Accumulator III. Negative number representation D. Control Unit IV. Arithmetic and Logic operations
- To make a memory of size 2048 × 8 using chips of size 128 × 4, the number of chips required is:
- Which of the following are sequential circuits? A. Flip-flop B. Multiplexer C. Counter D. Decoder E. Adder Choose the correct answer from the options given below:
- Techniques for performing I/O: A. Programmed I/O B. Interrupt-driven I/O C. Rotational I/O D. Direct memory access E. Channelized I/O Choose the correct answer from the options given below:
- In 16-bit 2's complement representation, the decimal number −28 is
- Simplify using a K-map: F(A, B, C, D) = Σm(3, 4, 5, 6, 7, 11, 15)
- A 3-bit synchronous counter uses T flip-flops P, Q, R (all clocked together) with inputs T_P = R, T_Q = P′ and T_R = Q′. If the initial state PQR is 000, what are the next three states?
- Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1 + R2, which values of R1 and R2 give an arithmetic overflow?
- Consider the Boolean expression F = (X + Y + Z)(X′ + Y)(Y′ + Z). Which of the following Boolean expressions is/are equivalent to F′ (the complement of F)? A. (X′ + Y′ + Z′)(X + Y′)(Y + Z′) B. XY′ + Z′ C. (X + Z′)(Y′ + Z…
- Which of the following statements is/are true? A. The processor has direct access to both primary and secondary memory. B. Primary memory stores the active instructions and data of the program being executed. C. Seconda…
- Match List I (8085 instructions) with List IIList I List II A. DAA I. Program Control Instruction B. LXI II. Interrupt instruction C. RST III. Data Movement Instruction D. JMP IV. Arithmetic Instruction
- The sequence of events during a typical instruction fetch is: A. Memory B. MBR C. MAR D. PC E. IR Choose the correct order from the options given below:
- Which one of the following types of memory is the fastest?
- The memory size for n address lines and m data lines is given by
- Simplify the following using a K-map: F(A, B, C, D) = Σ(0, 2, 5, 7, 8, 10, 13, 15)
- Consider an unpipelined machine with 10 ns clock cycles which uses four cycles for ALU operations and branches, and five cycles for memory operations. The relative frequencies of these operations are 40%, 20% and 40% re…
- Which of the statements is not true in regard to virtual memory?
- Which of the following is/are true for Dynamic RAM (DRAM)? 1. It is slower than static RAM (SRAM) 2. Packing density is higher than static RAM (SRAM) 3. It is faster than static RAM (SRAM) 4. It requires data refreshing…
- Which of the following statements is/are false? 1. The processor has direct access to both primary and secondary memory 2. Primary memory stores the active instructions and data for the program being executed on the pro…
- Match List I with List II (8085 addressing modes). Choose the correct answer from the options given below:List I List II a. Direct addressing I. MVI A, FFH b. Indirect addressing II. MOV A, B c. Register addressing III.…
- The correct sequence in the fetch–execute cycle is ______. I. Decode II. Fetch III. Execute
- Consider a memory system with addresses spaced at a distance of m (stride), T = bank cycle time and n = number of banks. Then the average data access time per word in a synchronous (interleaved) organisation is