All mock tests are FREE till 31 December — register to save your progress
Paper 2 CS · UNIT 02

Computer System Architecture – Previous Year Questions

224 questions from past UGC NET Paper 2 – Computer Science papers, each with the correct answer. Open any question for its explanation.

  1. Match List I (Boolean Algebra Law) with List II (Axioms)List I List II A. Absorption Law I. a + 1 = 1 B. Bounded Law II. a + 0 = a C. Identity Law III. a·(b + c) = (a·b) + (a·c) D. Distributive Law IV. a + (a·b) = a
    Answer: A. A-IV, B-I, C-II, D-III Paper 2 CS · December 2024
  2. Match List I with List IIList I List II A. (100110011)₂ I. Error detection code B. Complements II. CISC C. Parity Bits III. Negative number D. Variable length instruction IV. (133)₁₆
    Answer: B. A-IV, B-III, C-I, D-II Paper 2 CS · December 2024
  3. Which of the following are NOT data manipulation instructions? A. Call B. Load C. And D. Increment E. Shift Choose the correct answer from the options given below:
    Answer: B. A & B only Paper 2 CS · December 2024
  4. In the basic computer instruction format [I | opcode | address], which of the following do NOT represent memory-reference instructions? A. mode = 1, opcode = 010 B. mode = 0, opcode = 111 C. mode = 1, opcode = 111 D. mo…
    Answer: A. B & C only Paper 2 CS · December 2024
  5. Consider the number (45)ᵧ where y is the base of the number. Some of the possible values of y are given below. (A) 5 (B) 6 (C) 7 (D) 8 Choose the correct answer from the options given below:
    Answer: B. (B), (C) and (D) Only Paper 2 CS · June 2024 Re-Exam
  6. Find the correct sequence of the storage devices in descending order based on their access time. (A) Registers (B) Magnetic Disk (C) Magnetic Tapes (D) Main memory (E) Optical Disk Choose the correct answer from the opt…
    Answer: D. (C), (E), (B), (D), (A) Paper 2 CS · June 2024 Re-Exam
  7. A CPU has a 5-stage pipeline with stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle. Assume there are no pipeline stalls and the pipeline is initially empty. How…
    Answer: B. 14 Paper 2 CS · June 2024 Re-Exam
  8. Match List I (computing systems) with List II (working/output)List I List II (A) Half Adder (I) Has n inputs and 2ⁿ outputs (B) Decoder (II) CPU storage unit (C) Register (III) Used to store program at runtime (D) Main…
    Answer: C. (A)-(IV), (B)-(I), (C)-(II), (D)-(III) Paper 2 CS · June 2024 Re-Exam
  9. Consider the following statements regarding combinational and sequential circuits. (A) The output of a combinational circuit depends only on the current input. (B) The output of a combinational circuit depends on both t…
    Answer: B. (A) and (D) Only Paper 2 CS · June 2024 Re-Exam
  10. Arrange the following steps in the proper sequence for simplifying a Boolean function using a Karnaugh map (K-map). (A) Identify and group the largest possible clusters of 1's (B) Draw the K-map for the given Boolean fu…
    Answer: A. (B), (D), (A), (C) Paper 2 CS · June 2024 Re-Exam
  11. Match List I (Counter) with List II (uses/working)List I List II (A) N-bit Ring Counter (I) Uses universal clock (B) Synchronous Counter (II) Counts exactly N states (C) Asynchronous Counter (III) Counts 0 to 9 (D) Deci…
    Answer: C. (A)-(II), (B)-(I), (C)-(IV), (D)-(III) Paper 2 CS · June 2024 Re-Exam
  12. Consider the following statements regarding special-purpose registers. (A) The Program Counter (PC) keeps track of the next instruction to be executed. (B) The Instruction Register holds the address of the first instruc…
    Answer: A. (A) and (C) Only Paper 2 CS · June 2024 Re-Exam
  13. A multiprocessor system with 16 processors is used to execute a parallelizable task. The serial portion of the task takes 200 clock cycles and the parallel portion takes 800 clock cycles. When all 16 processors are used…
    Answer: A. 250 Paper 2 CS · June 2024 Re-Exam
  14. Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order. (A) Initiate DMA transfer request (B) Transfer data directly between peripheral and memory (C) Processor grants DMA contro…
    Answer: B. (A), (C), (B), (D) Paper 2 CS · June 2024 Re-Exam
  15. A vector processor with 16 lanes can perform an operation on 1024 elements, with each operation taking 5 clock cycles (pipelined). How many cycles are needed to complete the operation?
    Answer: A. 64 Paper 2 CS · June 2024 Re-Exam
  16. Which of the following circuits is used to store one bit of data?
    Answer: C. Flip-Flop Paper 2 CS · December 2023
  17. Identify the code sequence: 1010, 1011, 1001, 1000
    Answer: C. Gray Paper 2 CS · December 2023
  18. The microoperation which divides a signed binary number by 2 is:
    Answer: C. Arithmetic shift right Paper 2 CS · December 2023
  19. A program that is used by other routines to accomplish a particular task is called:
    Answer: D. Subroutine Paper 2 CS · December 2023
  20. A system bus in which each data item is transferred during a time slice known in advance to both the source and destination units is called:
    Answer: D. Synchronous bus Paper 2 CS · December 2023
  21. The average time required to reach a storage location in memory and obtain its contents is called:
    Answer: A. Access time Paper 2 CS · December 2023
  22. The interface(s) that provide I/O transfer of data directly to and from the memory unit and a peripheral is/are termed: (A) DMA (Direct Memory Access) (B) IOP (Input-Output Processor) (C) Serial Interface (D) Parallel I…
    Answer: C. (A) and (B) Only Paper 2 CS · December 2023
  23. Which of the following is/are main memory? (A) Virtual memory (B) Cache memory (C) RAM (D) SSD Choose the correct answer from the options given below:
    Answer: B. (B) and (C) Only Paper 2 CS · December 2023
  24. Which of the following statements is/are NOT CORRECT about NUMA? (A) LOAD and STORE instructions are used to access remote memory. (B) There is a single address space visible to all CPUs. (C) Access to local memory is s…
    Answer: D. (C) and (D) Only Paper 2 CS · December 2023
  25. Match List I with List II (basic computer instructions)List I List II (a) SZA (I) Increment M and skip if zero (b) SKI (II) Skip if AC is negative (c) SNA (III) Skip if input flag is on (d) ISZ (IV) Skip if AC is zero
    Answer: B. (a)-(IV), (b)-(III), (c)-(II), (d)-(I) Paper 2 CS · December 2023
  26. In the most general case, the computer needs to process each instruction with the following sequence of steps: (A) Calculate the effective address (B) Execute the instruction (C) Fetch the instruction from memory (D) Fe…
    Answer: B. (C), (E), (A), (D), (B) Paper 2 CS · December 2023
  27. What is the 4+4-bit binary fixed-point (two's complement) equivalent of −(3.72)₁₀?
    Answer: C. 1100.0100 Paper 2 CS · June 2023
  28. Let ⊕ denote XOR, and 1 and 0 the binary constants. F(P, Q) = ((1 ⊕ P) ⊕ (P ⊕ Q)) ⊕ ((P ⊕ Q) ⊕ (Q ⊕ 0)). Which of the following is equivalent to F?
    Answer: D. complement of (P ⊕ Q) Paper 2 CS · June 2023
  29. A processor chip is used for an application in which 30% of execution time is spent on floating-point addition. For the new model, the design team redesigns the floating-point adder to make it twice as fast. What is the…
    Answer: C. 1.18 Paper 2 CS · June 2023
  30. A 256 Mb DRAM is organised as a 32M × 8 memory externally and as a 16K × 16K square array internally. Each row must be refreshed at least once every 50 ms, and refreshing one row takes 100 ns. What fraction of the total…
    Answer: B. 3.3% Paper 2 CS · June 2023