Arrange the following in terms of their capacity from smallest to largest:
A. L3 Cache
B. L1 Cache
C. CPU Register
D. L2 Cache
Choose the correct answer from the options given below:
Pick an option to check yourself, or open the answer below.
Show answer & explanation
Correct answer: C. C, B, D, A
Explanation
In the memory hierarchy, capacity increases as access speed decreases, moving away from the CPU. CPU registers are the smallest (a few bytes to a few words), followed by the L1 cache (tens of KB), then the larger L2 cache (hundreds of KB to a few MB), and finally the largest of the four, the L3 cache (several MB, shared across cores). This gives the smallest-to-largest order C, B, D, A.More Computer System Architecture questions
- The combination of selection lines for sending the input I14 to output in the following multiplexer is? (A 64×1 MUX with inputs I0...I63 an…
- Match the LIST-I with LIST-IILIST-I LIST-II A. FDM I. has four possible Minterms B. Digital Circuits II. Frequency Division Multiplexing C.…
- For sending input I6 on the output line of a 8×1 multiplexer, (an 8×1 MUX with inputs I0...I7, selection lines S2, S1, S0, driving output O…
- The term "double buffered" is used in which of the following?
- What does "Amdahl's Law" describe in the context of parallel processing?
- The transformation of data from main memory to cache memory is referred as: