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Unit 2 · Computer System Architecture Paper 2 CS · September 2022

A 4-stage pipeline has stage delays of 150, 120, 160 and 140 ns. Registers between the stages have a delay of 5 ns. Assuming a constant clocking rate, the total time required to process 1000 data items is

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Correct answer: B. 165.5 μs

Explanation

Clock = max stage + register = 160 + 5 = 165 ns. Time = (4 + 999) × 165 ns = 165,495 ns ≈ 165.5 μs (the paper prints the unit as ms).

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