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Unit 2 · Computer System Architecture Paper 2 CS · July 2018

In RS flip-flop, the output of the flip-flop at the time (t+1) is the same as the output at time t, after the occurrence of a clock pulse if :

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Correct answer: D. S=R=0

Explanation

S = R = 0 is the hold state: Q(t+1) = Q(t).

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