UGC NET · PAPER 2
UGC NET Paper 2 Computer Science – Unit 5: System Software and Operating System PYQ (June 2023)
Q9. Given below are two statements: one is labelled as Assertion A and the other is labelled as Reason R.
Assertion A: I/O protection is ensured by a hardware trap.
Reason R: I/O interrupts are caused by conditions like I/O completion and device malfunction occurring within the I/O devices.
Assertion A: I/O protection is ensured by a hardware trap.
Reason R: I/O interrupts are caused by conditions like I/O completion and device malfunction occurring within the I/O devices.
- Both A and R are true and R is the correct explanation of A
- Both A and R are true but R is NOT the correct explanation of A
- A is true but R is false
- A is false but R is true
Q13. Consider the following statements:
S1: The LRU page-replacement algorithm suffers from Belady's anomaly.
S2: Shortest-remaining-time-first scheduling may cause starvation.
S3: The stack is shared by all threads in a process.
S1: The LRU page-replacement algorithm suffers from Belady's anomaly.
S2: Shortest-remaining-time-first scheduling may cause starvation.
S3: The stack is shared by all threads in a process.
- S1, S2 and S3 are true
- S1, S3 are false and S2 is true
- S1, S2 are false and S3 is true
- S1, S2 and S3 are false
Q20. Given below are two statements: one is labelled as Assertion A and the other is labelled as Reason R.
Assertion A: A process invokes a library function to create a thread.
Reason R: Threads make system calls to convey their resource and I/O requirements to the kernel.
Assertion A: A process invokes a library function to create a thread.
Reason R: Threads make system calls to convey their resource and I/O requirements to the kernel.
- Both A and R are true and R is the correct explanation of A
- Both A and R are true but R is NOT the correct explanation of A
- A is true but R is false
- A is false but R is true
Q26. With respect to virtual memory:
Statement I: Address translation is performed for every logical address used during the execution of a program.
Statement II: A program can execute only when all of its components are loaded in memory.
Statement I: Address translation is performed for every logical address used during the execution of a program.
Statement II: A program can execute only when all of its components are loaded in memory.
- Both Statement I and Statement II are correct
- Both Statement I and Statement II are incorrect
- Statement I is correct but Statement II is incorrect
- Statement I is incorrect but Statement II is correct
Q38. A virtual memory system uses the first-in first-out page replacement policy and allocates a fixed number of frames to a process.
Assertion A: Increasing the number of page frames allocated to a process sometimes increases the page fault rate.
Reason R: Some programs do not exhibit locality of reference.
Assertion A: Increasing the number of page frames allocated to a process sometimes increases the page fault rate.
Reason R: Some programs do not exhibit locality of reference.
- Both A and R are true and R is the correct explanation of A
- Both A and R are true but R is NOT the correct explanation of A
- A is true but R is false
- A is false but R is true
Q42. Consider the following arrival and burst times for three processes P0, P1, P2. The pre-emptive shortest job first algorithm is used, and scheduling is carried out only at the arrival or completion of a process. What is the average waiting time for the three processes?
| Process | Arrival time | Burst time |
|---|---|---|
| P0 | 0 ms | 7 |
| P1 | 1 ms | 3 |
| P2 | 2 ms | 7 |
- 3 ms
- 3.67 ms
- 4.47 ms
- 4 ms
Q46. Match List I with List II
| List I | List II |
|---|---|
| A. RAID level 2 | I. Bit interleaved parity |
| B. RAID level 4 | II. Block interleaved distributed parity |
| C. RAID level 5 | III. Error correcting parity |
| D. RAID level 3 | IV. Block interleaved parity |
- A-IV, B-III, C-I, D-II
- A-III, B-IV, C-II, D-I
- A-III, B-I, C-II, D-IV
- A-I, B-III, C-IV, D-I
Q54. Match List I with List II
| List I | List II |
|---|---|
| A. Critical region | I. Hoare's monitor |
| B. Wait/signal | II. Mutual exclusion |
| C. Working set | III. Principle of locality |
| D. Deadlock | IV. Circular wait |
- A-IV, B-I, C-III, D-II
- A-II, B-I, C-III, D-IV
- A-I, B-II, C-III, D-IV
- A-IV, B-III, C-I, D-II
Q58. At a particular time of computation, the value of a counting semaphore is 7. Then 20 P operations and x V operations were completed on this semaphore. If the final value of the semaphore is 5, x will be
- 15
- 22
- 18
- 13
Q78. Requests to access cylinders occur in the sequence 4, 34, 10, 7, 19, 73, 2, 15, 6, 20. The head is currently at cylinder 50, and it takes 1 ms to move between adjacent cylinders. What is the time taken to satisfy all requests with the shortest-seek-time-first policy?
- 119 ms
- 120 ms
- 142 ms
- 146 ms
Directions (Q91–95): Consider the following program fragment that deals with a table T with 17 rows and 1024 columns, computing an average for each column and printing it (i is the row index and j is the column index):
for j = [0...1023] {
temp = 0;
for i = [0...16]
temp = temp + T[i][j];
print(temp / 17.0);
}T[i][j] and temp are 32-bit floating-point values and memory is word addressable. temp is kept in a processor register, so accessing temp does not involve a memory reference. The main memory is paged and holds 16 pages of 1024 words each. The page replacement policy is least recently used (LRU). Unless stated otherwise, T is stored in the virtual address space in row-major format.
Q91. Consider now that T is stored in column-major format. What is the main memory hit ratio?
- 80%
- 95.6%
- 97.8%
- 99.9%
Q92. Consider that T is stored in column-major format. How many page faults will be encountered?
- 14
- 15
- 16
- 17
Q93. With T stored in row-major format, how many page faults will be encountered?
- 16,402
- 17,408
- 18,208
- 18,608
Q94. What is the ratio of page faults for the row-major to the column-major arrangement?
- 1024 : 1
- 1301 : 1
- 1240 : 1
- 9107 : 8
Q95. With T stored in row-major format, what is the main memory hit ratio?
- 0
- 1
- 2
- 3