UGC NET · PAPER 2
UGC NET Paper 2 Computer Science – Unit 2: Computer System Architecture PYQ (June 2025)
Q6. The transformation of data from main memory to cache memory is referred as:
- Data exchange
- Data transformation
- Mapping
- Matching
Q9. Consider the Boolean expression A(x, y, z) = x(y′z)′. Which of the following is the complete sum-of-products form of the given Boolean expression?
- xyz + x′yz′ + x′y′z′
- xyz′ + x′yz′ + x′y′z′
- xyz′ + xy′z + x′y′z′
- xyz + xyz′ + xy′z′
Q11. Match List I with List II
| List I | List II |
|---|---|
| A. Address Space | I. Associative Mapping |
| B. Memory Space | II. Logical address |
| C. Cache Memory | III. Physical address |
| D. Segmented Program | IV. Virtual address |
- A-IV, B-III, C-I, D-II
- A-I, B-II, C-IV, D-III
- A-III, B-IV, C-I, D-II
- A-II, B-IV, C-I, D-III
Q29. Binary equivalent to (A0F)16 is:
- 111000111
- 101001111
- 101000001111
- 111100001010
Q46. The write operation in an I/O operation does the following
- Transfer data from I/O device to memory
- Transfer data from memory to I/O device
- Transfer data from CPU register to memory
- Transfer data from CPU register to I/O device
Q51. Which of the following gates do NOT give output 1 when both the inputs are 0?
A. NAND gate
B. NOR gate
C. X-OR gate
D. X-NOR gate
Choose the correct answer from the options given below:
A. NAND gate
B. NOR gate
C. X-OR gate
D. X-NOR gate
Choose the correct answer from the options given below:
- A, B Only
- B, C Only
- C, D Only
- C Only
Q73. The computer needs to process each instruction with the following sequence of steps:
A. Calculate the effective address
B. Fetch the instruction from memory
C. Decode the instruction
D. Fetch the operands from the memory
E. Execute the instruction
Choose the correct answer from the options given below:
A. Calculate the effective address
B. Fetch the instruction from memory
C. Decode the instruction
D. Fetch the operands from the memory
E. Execute the instruction
Choose the correct answer from the options given below:
- A, B, C, D, E
- B, A, D, A, E
- B, C, A, D, E
- C, B, A, D, E
Q79. Which of the following statements are true?
A. In the write-through policy, only the cache is updated
B. In the write-back policy, both cache and main memory are updated
C. Cache coherence problems exist in multiprocessors with private caches because of the need to share writable data
D. Cache coherence problem can be solved by means of hardware-only scheme
Choose the correct answer from the options given below:
A. In the write-through policy, only the cache is updated
B. In the write-back policy, both cache and main memory are updated
C. Cache coherence problems exist in multiprocessors with private caches because of the need to share writable data
D. Cache coherence problem can be solved by means of hardware-only scheme
Choose the correct answer from the options given below:
- A, B Only
- B, C Only
- C, D Only
- A, B, C Only
Q89. The right sequence of a CPU program to input data will be:
A. Read status register
B. Check flag bit
C. Read data register
D. Transfer data to memory
Choose the correct answer from the options given below:
A. Read status register
B. Check flag bit
C. Read data register
D. Transfer data to memory
Choose the correct answer from the options given below:
- A, B, C, D
- B, A, C, D
- C, B, A, D
- A, C, B, D
Q90. The right sequence of suboperations that are performed in an arithmetic pipeline (floating-point addition) is
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below:
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below:
- D, A, B, C
- D, B, A, C
- B, C, A, D
- B, C, D, A