UGC NET · PAPER 2
UGC NET Paper 2 Computer Science – Unit 2: Computer System Architecture PYQ (June 2024 (Cancelled Exam))
Q11. The instruction LD ADR(X), equivalent to AC ← M[ADR + XR], is in:
- Direct addressing mode
- Indirect addressing mode
- Index addressing mode
- Immediate addressing mode
Q31. The instructions
ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
evaluate X = (A + B) * (C + D) using which of the following?
ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
evaluate X = (A + B) * (C + D) using which of the following?
- 3-address instructions
- 2-address instructions
- 1-address instructions
- RISC instructions
Q34. The Boolean expression for F(A, B, C) = Σm(0, 2, 6) with don't-cares d(A, B, C) = Σ(1, 3, 5) would be:
- A′C′ + BC′
- B + AC′
- A + BC′
- A′ + BC′
Q36. A computer system has a cache access time of 100 ns, a main-memory access time of 1100 ns and a hit ratio of 0.9. The average access time would be:
- 200 ns
- 190 ns
- 210 ns
- 120 ns
Q42. Match List I (Boolean expression) with List II (dual of the Boolean expression)
| List I | List II |
|---|---|
| A. x·y + 0 | I. (x̄ + 0)·(ȳ·z) |
| B. x̄·1 + (ȳ + z) | II. (x + y)·1 |
| C. x̄·(ȳ + 0) | III. x̄ + ȳ·1 |
| D. x·1 + (y + z̄) | IV. (x + 0)·(y·z̄) |
- A-III, B-IV, C-II, D-I
- A-III, B-IV, C-I, D-II
- A-II, B-I, C-III, D-IV
- A-II, B-I, C-IV, D-III
Q65. The I/O method in which memory addresses and I/O addresses are distinct is called
A. Isolated I/O
B. Memory-mapped I/O
C. Strobe control
D. Handshaking
E. Interrupt
Choose the most appropriate answer from the options given below:
A. Isolated I/O
B. Memory-mapped I/O
C. Strobe control
D. Handshaking
E. Interrupt
Choose the most appropriate answer from the options given below:
- A, B Only
- C, D Only
- C, E Only
- B, E Only
Q68. Arrange the following from fastest to slowest:
A. DRAM
B. SRAM
C. CPU registers
D. Magnetic tapes
E. Hard disk
Choose the correct answer from the options given below:
A. DRAM
B. SRAM
C. CPU registers
D. Magnetic tapes
E. Hard disk
Choose the correct answer from the options given below:
- A, B, C, D, E
- C, B, A, D, E
- C, D, B, A, E
- B, C, D, A, E
Q70. Regarding the interrupt service subroutine, consider the following tasks:
A. Turn the interrupt facility on
B. Service the device whose flag is set
C. Save the contents of processor registers
D. Check which flag is set
E. Restore the contents of processor registers
Choose the correct answer from the options given below:
A. Turn the interrupt facility on
B. Service the device whose flag is set
C. Save the contents of processor registers
D. Check which flag is set
E. Restore the contents of processor registers
Choose the correct answer from the options given below:
- A, D, C, B, E
- D, A, B, C, E
- C, D, B, E, A
- B, D, A, C, E
Q77. Match List I with List II
| List I | List II |
|---|---|
| A. Complement | I. Adder |
| B. E-OR | II. Instruction decoding |
| C. Accumulator | III. Negative number representation |
| D. Control Unit | IV. Arithmetic and Logic operations |
- A-I, B-II, C-III, D-IV
- A-III, B-II, C-I, D-IV
- A-III, B-I, C-IV, D-II
- A-IV, B-II, C-III, D-I
Q85. To make a memory of size 2048 × 8 using chips of size 128 × 4, the number of chips required is:
- 8
- 16
- 32
- 64
Q86. Which of the following are sequential circuits?
A. Flip-flop
B. Multiplexer
C. Counter
D. Decoder
E. Adder
Choose the correct answer from the options given below:
A. Flip-flop
B. Multiplexer
C. Counter
D. Decoder
E. Adder
Choose the correct answer from the options given below:
- B, D Only
- A, C Only
- C, E Only
- D, A Only
Q88. Techniques for performing I/O:
A. Programmed I/O
B. Interrupt-driven I/O
C. Rotational I/O
D. Direct memory access
E. Channelized I/O
Choose the correct answer from the options given below:
A. Programmed I/O
B. Interrupt-driven I/O
C. Rotational I/O
D. Direct memory access
E. Channelized I/O
Choose the correct answer from the options given below:
- A and C Only
- A, B, and D Only
- A, D and E Only
- B and E Only